CPU Design/Verification - Intern

Positions are open for Co-op/internship in the areas of CPU RTL design and verification from unit level to chip level.

We are looking for candidates who have taken modern CPU microarchitecture related courses.

Responsibilities

• Design Intern:
• Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specification
• Development, assessment, and refinement of RTL design to target power, performance, area, and timing goals
• Validation - support test bench development and simulation for functional and performance verification
• Performance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performance
• Design delivery - work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and power
• Verification Intern:
• Work closely with architecture and RTL designers on verifying the functionality correctness of the design
• Reviewing Architecture and Design Specifications
• Develop test plans and test environments
• Develop tests in assembly, C/C++, or vectors according to test plans
• Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered
• Develop checkers in SystemVerilog or C-base transactors to verify the design
• Write assertions and apply formal verification to the designImplementing test benches, generating directed/constrained random tests
• Debugging failures, running simulations, tracking bugs
• Handling schedules and supporting multi-functional engineering effortAssisting in verification flows, automation scripts and regressions
  
  
  

Requirements

• Thorough knowledge of modern CPU microarchitecture in the following areas: Instruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, cache and memory subsystems.
• Knowledge of SystemVerilog
• Experience with simulators and waveform debugging tools
• Knowledge of logic design principles along with timing and power implications
• Understanding of low power microarchitecture techniques
• Understanding of high performance techniques and trade-offs in a CPU microarchitecture
• Experience in C or C++ programming
• Experience using an interpretive language such as Perl or Python
• Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
• Ability to work well in a team and be productive under aggressive schedules.
  
  
  

Education And Experience

• PhD, Master’s Degree or Bachelor’s Degree in technical subject area.