Senior ASIC Design Verification Engineer

Cornelis Networks is a technology leader delivering purpose-built, high-performance fabrics accelerating High Performance Computing, High Performance Data Analytics, and Artificial Intelligence workloads in the Cloud and in the Data Center.

The company s products enable scientific, academic, governmental, and commercial customers to solve some of the world s toughest challenges by efficiently focusing the computational power of many processing devices at scale on a single problem, simultaneously improving both result accuracy and time-to-solution for their most complex application workloads. Cornelis Networks delivers its end-to-end interconnect solutions worldwide through an established set of server OEM and channel partners.

Cornelis Networks is hiring Mid-Level and Senior ASIC Verification Engineers with advanced skills and knowledge in key areas required to verify world-class SoCs to be deployed in high performance computing, high performance data analytics, and artificial intelligence interconnect solutions. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC design, emulation and post-silicon teams towards creating a first-pass silicon success. A preferrable candidate will have 10 + years of relevant experience in networking hardware verification, proven expertise in verifying one or more of the following: 50G, 100G, 400G Ethernet MAC/PCS protocols, UDP, TCP/IP, RDMA/RoCE, IPSec. and their application in high-speed data processing/networking.

Key Responsibilities:

• Participate in ground up development of UVM environments to verify RTL at block, unit, and SoC levels
• Develop and execute functional tests according to verification test plans
• Instrument TB for functional and code coverage and drive to closure based on the coverage metrics
• Collaborate with cross-functional teams like design, software, emulation and silicon validation teams towards ensuring the highest design quality

Minimum Qualifications (Please do not apply if you do not meet the following minimum requirements):

• 10 + years of post-college experience with the following:

• • Writing code using System Verilog Language
  • Verification for complex SoCs that include multiple clock and reset domains, using VCS or equivalent simulation tools
  • Debugging fails to the line of RTL, closing out bug fixes, using Verdi or equivalent debug tools

• Experience in ground up testbench development
• Experience with revision control systems like Git or SVN etc.
• B. S. Degree in Computer Engineering, Computer Science, or Electrical Engineering

Preferred Qualifications:

• M. S. Degree in Computer Engineering, Computer Science, or Electrical Engineering
• 10 + years of relevant experience in networking hardware verification, proven expertise in verifying 50G, 100G, 400G Ethernet MAC/PCS protocols, TCP/IP, RDMA/RoCE, IPSec. and their application in high-speed data processing/networking
• One or more scripting languages (TCL, Python, Perl, Shell-scripting)
• Track record of first-pass success in ASIC and Systems

Job Location:

For this position, Cornelis Networks fully supports remote employees who live within the United States and can travel to our corporate offices in Chesterbrook, PA periodically for in-person collaboration.

Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law.

Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services.