DSP SYSTEMS ENGINEER

• Education: Master s or PhD degree with an emphasis in ASIC (Application-Specific Integrated Circuit) design and DSP.
• Experience: A minimum of five years of professional experience in RTL design specifically using Verilog and System Verilog.
• Expertise in DSP: Proven experience in the development and optimization of DSP-related RTL blocks and the subsequent testing and verification processes.
• Communication Protocol Knowledge: Prior exposure to the physical layer of communication chips such as Wi-Fi, BLE, GNSS, or cellular technologies is highly desirable.
• Technical Skills: Strong background in designing state machines, data paths, arbitration, and clock domain crossing logic with practical experience in logic synthesis support, FPGA implementation, and timing constraints.
• DFT Knowledge: Familiarity with Design for Test strategies, understanding scan concepts, and writing DFT-friendly RTL.
• Power Management: Competence in utilizing Unified Power Format for simulation, synthesis, and electrical rule checking, along with accurate power estimation methodologies.
• Collaboration Skills: A collaborative team player with excellent interpersonal, communication, and writing skills, capable of effectively presenting complex technical concepts.

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