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Verification Engineer Intermediate

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We are looking for Verification Engineer Intermediate for our client in Markham, ON
Job Title: Verification Engineer Intermediate
Job Location: Markham, ON
Job Type: Contract
Job Description:
Responsibilities:
  • Help create a test plan that outlines required verification work for the project.
  • Produce verification code that tests RTL design functionality using UVM (Digital design verification framework built using System Verilog) as per test plan.
  • Write cover points to make sure verification items are properly exercised.
  • Work on necessary debugging of verification code; fix tests to hit cover points if coverage is failing.
  • Use Formal Verification techniques as needed.
  • Manage and monitor regressions (regular repeated runs of the same set of mostly random tests) for team s blocks and fix errors in failing tests.
  • Generate and analyze coverage reports to ensure exhaustive verification of the design and all possible end-cases.
  • Write and edit csh, perl, python or ruby scripts to automate verification.
  • Regular review and sign-off of design verification work at key project milestones.
Requirements:
  • Solid fundamental understanding of Computer Architecture and Digital Design concepts.
  • Strong background in OOP coding techniques.
  • Experience with Verilog or SystemVerilog; experience with UVM.
  • Familiarity with scripting languages: perl or tcl or ruby or Bash or python, etc.
  • Strong analytical skills and attention to detail.
  • Excellent written and verbal communication skills.
Growth Opportunities:
  • Will get an understanding of how TLBs, data caches, data transfer protocols, data compression algorithms, threading, pipelining, timing analysis, and other computer architecture concepts are used in commercial ASIC design and verification.
  • Opportunity to learn end to end Graphics Accelerator Pipeline and Graphics rendering concepts such as rasterization and ray tracing.
  • Will build expertise in Verilog, System Verilog, and OOP techniques used in complex design development.
  • Universal Verification Methodology (UVM), and System Verilog Assertion Based Verification (ABV).
  • Exposure to Formal Verification Techniques.
  • Work with sophisticated industry standard tools such as Synopsys VCS, Verdi, VC Formal, etc.
  • Be directly involved in the development of next-generation computer products.
  • Develop communication skills further in a professional environment; meet and connect with industry experts and professionals.
Academic Credentials:
  • Bachelor s Degree in Computer, Electrical, Mechatronics Engineering or Engineering Science or similar.
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