Analog Layout Engineer

Role: Analog Layout Engineer
Location: Santa Clara, CA (Onsite)

Job Description:

We are seeking a Senior Layout Designer to lead the layout of high-performance analog cores such as analog-to-digital converters (ADC), digital-to-analog converters (DAC), phase-locked loops (PLL), and transceivers. The position involves working with advanced CMOS integrated circuits across cutting-edge process nodes like 3nm, 5nm, 7nm, and 16nm, adhering to industry best practices.

Responsibilities:

• Lead the layout of high-performance, high-speed CMOS integrated circuits.
• Execute the layout of analog blocks (e.g., ADCs, DACs, PLLs) using foundry CMOS processes.
• Perform layout for advanced FinFET process nodes, ensuring optimal performance and manufacturability.
• Set up and debug LVS, DRC, and ERC environments using industry-standard EDA tools from Cadence and Mentor.
• Collaborate with distributed design teams to achieve successful chip assembly and tape-out.
• Utilize advanced layout techniques (e.g., common centroid, shielding, thermal-aware layout) to address critical design challenges such as electromigration and noise.
• Floor planning, block-level routing, and top-level chip integration for high-performance analog designs.

Qualifications:

• Proficient in using EDA tools from Cadence, Mentor, and Synopsys.
• Expertise in setting up and debugging LVS, DRC, and ERC environments.
• Experience in the layout of high-performance analog blocks (e.g., ADCs, references, DACs, PLLs).
• Strong knowledge of advanced CMOS processes (3nm, 5nm, 7nm, 16nm).
• Familiarity with FinFET process nodes and high-performance layout techniques.
• Ability to work with distributed teams, contributing to collaborative design environments.
• Knowledge of Skill code and layout automation is a plus.
• Strong written and verbal communication skills.
• Minimum of 10+ years of experience in analog layout design for silicon chips in mass production.

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