Design Verification Engineer

Job Title : Design Verification Engineer
Location: Bay Area, CA / Austin, TX ( Onsite )
Duration/Term: Long Term Contract

Job Summary:

We are seeking a highly experienced Verification Engineer with a strong background in constructing scalable, configurable, and reusable DV/Performance verification environments. The ideal candidate will have experience in ASIC design/verification at the IP, Subsystem, or SOC level, and proficiency in System Verilog, System C, and UVM models.

Key Responsibilities:

• DV/Performance Verification Environment: Build scalable and reusable verification environments focused on performance and design verification.
• ASIC Design/Verification: Extensive experience in ASIC design/verification, including work at the IP, Subsystem, and SOC level.
• Modeling and Simulation: Write System Verilog and/or System C models for simulation to ensure the design performs as expected.
• UVM Models and Methodology: Develop UVM models, checkers, and stimulus. Construct UVM register models and apply constrained random methodology in UVM test environments.
• Test Plan Development: Compose test plans and validation vectors to ensure comprehensive functional verification.
• Design for Verification (DFV): Apply assertion-based design strategies, code coverage, functional coverage, test planning, gate-level simulation, and back-annotation.
• Verification Flow Proficiency: Expertise in high-level verification flows such as System Verilog (SV), UVM, and C++, along with familiarity with industry-standard verification tools.
• Communication and Problem-Solving: Strong written and oral communication skills, with a proven ability to resolve complex verification issues.

Qualifications:

• Experience: Rich experience in constructing highly scalable and configurable DV/Performance verification environments.
  Experience in ASIC design/verification related to IP, Subsystem, or SOC levels.
• Technical Expertise: Proficient in System Verilog, System C, and UVM modeling.
  Hands-on experience with assertion-based design strategies, code coverage, and functional coverage.
• Problem-Solving Skills: Excellent problem-solving abilities to identify and resolve verification challenges effectively.

Key Skills: DV/Performance Verification, ASIC Design, System Verilog, System C, UVM, Verification Flows, Test Planning, Code Coverage, Functional Coverage, Gate-Level Simulation, Back-Annotation.

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