Silicon Design Verification Engineer III
About Ascendion
Ascendion is a full-service digital engineering solutions company. We make and manage software platforms and products that power growth and deliver captivating experiences to consumers and employees. Our engineering, cloud, data, experience design, and talent solution capabilities accelerate transformation and impact for enterprise clients. Headquartered in New Jersey, our workforce of 6,000+ Ascenders delivers solutions from around the globe. Ascendion is built differently to engineer the next.
Ascendion | Engineering to elevate life
We have a culture built on opportunity, inclusion, and a spirit of partnership. Come, change the world with us:
- Build the coolest tech for world s leading brands
- Solve complex problems and learn new skills
- Experience the power of transforming digital engineering for Fortune 500 clients
- Master your craft with leading training programs and hands-on experience
Experience a community of change makers!
Join a culture of high-performing innovators with endless ideas and a passion for tech. Our culture is the fabric of our company, and it is what makes us unique and diverse. The way we share ideas, learning, experiences, successes, and joy allows everyone to be their best at Ascendion.
About the Role:
- We are looking for an exceptional Silicon Design Verification Engineer in San Francisco Bay area.
- This role is within the team which is currently working in the Reality Lab space within the AR/VR world and creating the graphics.
- This role requires hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology.
Job Title: Silicon Design Verification Engineer III
Key Responsibilities:
- Work with researchers and architects defining verification plans for each of the different core IP.
- Define and track detailed test plans for the different modules and top levels.
- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
- Debug, root-cause and resolve functional failures in the design, partnering with the Design team
- Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.
- Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.
Minimum Qualifications:
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- 5+ years of hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology.
- Experience writing python scripts
- Ability to write from scratch UVM methods
Preferred Qualifications:
- Master's degree or PhD in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- 10+ years of hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology.
- Simulation or relation experience is a plus.
Location: San Francisco Bay Area, CA
Salary Range: The salary for this position is between $145,600 $200,241 annually. Factors which may affect pay within this range may include geography/market, skills, education, experience, and other qualifications of the successful candidate.
Benefits: The Company offers the following benefits for this position, subject to applicable eligibility requirements: [medical insurance] [dental insurance] [vision insurance] [401(k) retirement plan] [long-term disability insurance] [short-term disability insurance] [5 personal days accrued each calendar year. The Paid time off benefits meet the paid sick and safe time laws that pertains to the City/ State] [10-15 days of paid vacation time] [6 paid holidays and 1 floating holiday per calendar year] [Ascendion Learning Management System]
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