Key Responsibilities:
Perform full-custom layout of Analog and RF circuits, including amplifiers, mixers, oscillators, and other high-frequency components.
Work closely with circuit designers to ensure optimal layout for performance, area, and manufacturability.
Conduct physical verification (DRC, LVS, ERC, and ANT) and debugging of issues to meet foundry requirements.
Optimize layout for matching, shielding, isolation, and noise reduction techniques.
Perform parasitic extraction analysis to optimize circuit performance and reduce layout-induced variations.
Ensure adherence to process design rules and compliance with manufacturing constraints.
Work in collaboration with the CAD and design teams to enhance design methodologies and automation.
Support tape-out activities, ensuring designs meet tape-out quality standards.
Qualifications & Skills:
Bachelor s or Master s degree in Electrical Engineering, Microelectronics, or a related field.
3+ years of experience in Analog/RF IC layout design.
Proficiency in Cadence Virtuoso, Calibre, Assura, or similar EDA tools.
Strong understanding of CMOS, BiCMOS, and SOI process technologies.
Experience with high-frequency layout techniques, including matching, symmetry, shielding, and parasitic-aware design.
Knowledge of EM/IR drop analysis and ESD considerations.
Strong problem-solving skills and ability to debug complex layout-related issues.
Excellent communication and teamwork skills, with the ability to work effectively in a collaborative environment.
Preferred Qualifications:
Experience with RFIC/analog mixed-signal layout for advanced technology nodes (e.g., 7nm, 5nm, 3nm).
Familiarity with PDK development and automation scripting (SKILL, Python, or Perl).
Understanding of foundry tape-out processes and post-layout simulations
Key Responsibilities:
Perform full-custom layout of Analog and RF circuits, including amplifiers, mixers, oscillators, and other high-frequency components.
Work closely with circuit designers to ensure optimal layout for performance, area, and manufacturability.
Conduct physical verification (DRC, LVS, ERC, and ANT) and debugging of issues to meet foundry requirements.
Optimize layout for matching, shielding, isolation, and noise reduction techniques.
Perform parasitic extraction analysis to optimize circuit performance and reduce layout-induced variations.
Ensure adherence to process design rules and compliance with manufacturing constraints.
Work in collaboration with the CAD and design teams to enhance design methodologies and automation.
Support tape-out activities, ensuring designs meet tape-out quality standards.
Qualifications & Skills:
Bachelor s or Master s degree in Electrical Engineering, Microelectronics, or a related field.
3+ years of experience in Analog/RF IC layout design.
Proficiency in Cadence Virtuoso, Calibre, Assura, or similar EDA tools.
Strong understanding of CMOS, BiCMOS, and SOI process technologies.
Experience with high-frequency layout techniques, including matching, symmetry, shielding, and parasitic-aware design.
Knowledge of EM/IR drop analysis and ESD considerations.
Strong problem-solving skills and ability to debug complex layout-related issues.
Excellent communication and teamwork skills, with the ability to work effectively in a collaborative environment.
Preferred Qualifications:
Experience with RFIC/analog mixed-signal layout for advanced technology nodes (e.g., 7nm, 5nm, 3nm).
Familiarity with PDK development and automation scripting (SKILL, Python, or Perl).
Understanding of foundry tape-out processes and post-layout simulations