ASIC Physical Design Engineer

Triple Crown is a leading provider of hardware, embedded, software, and mechanical engineering talent. Businesses and technology teams, from Fortune 500 enterprises to emerging startups, rely on our ability to rapidly place the developers, architects, coders, and designers who engineer digital transformation and growth.

CONTRACT Position: 12+ Months

Location: Austin, TX OR Poughkeepsie, NY (potential for partial remote flexibility)

We are seeking an experienced ASIC Physical Design Engineer to contribute to the full physical design flow of ASIC projects. The ideal candidate will have a strong background in VLSI design, experience with advanced physical design techniques, and proficiency with industry-standard EDA tools. You will be involved in transforming high-level ASIC designs into optimized, manufacturable, and high-performance chip layouts.

Job Description:

• As a Physical Design / Integration / Clocking / Timing Engineer, you will be responsible for the physical and electrical design and development of high-frequency microprocessor and ASIC chips at the chiplet and chip hierarchies.
• Design, coordinate and manage clock and power delivery networks across all levels.
• Optimize buffering and wiring to meet power, timing, yield, and manufacturability constraints.
• Collaborate with internal EDA team/external tool vendors to develop and optimize tools and methodologies.
• Must have 10+ years of experience in high-frequency processor physical design.
• Scripting skills (Python, Tcl, SKILL, etc.).
• Ability to work well in a team and be productive under aggressive schedules.
• Strong communication skills.
• Understanding of Agile development processes.
• Experience with Cadence Innovus, Tempus, Voltus, and/or IP integration (HBM, PCIe) for ASIC roles.
• Demonstrated ability to effectively team with a cross-site, multidisciplinary, international team.

Skills:

• Backend Physical Design
• ASIC
• Place & Route
• Cadence InnovTempus
• LVS/DRC
• Python is a plus

Benefits:

• Paid weekly!
• Health, Dental and Vision Insurance
• 401k

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Triple Crown is a leading provider of hardware, embedded, software, and mechanical engineering talent. Businesses and technology teams, from Fortune 500 enterprises to emerging startups, rely on our ability to rapidly place the developers, architects, coders, and designers who engineer digital transformation and growth.

CONTRACT Position: 12+ Months

Location: Austin, TX OR Poughkeepsie, NY (potential for partial remote flexibility)

We are seeking an experienced ASIC Physical Design Engineer to contribute to the full physical design flow of ASIC projects. The ideal candidate will have a strong background in VLSI design, experience with advanced physical design techniques, and proficiency with industry-standard EDA tools. You will be involved in transforming high-level ASIC designs into optimized, manufacturable, and high-performance chip layouts.

Job Description:

• As a Physical Design / Integration / Clocking / Timing Engineer, you will be responsible for the physical and electrical design and development of high-frequency microprocessor and ASIC chips at the chiplet and chip hierarchies.
• Design, coordinate and manage clock and power delivery networks across all levels.
• Optimize buffering and wiring to meet power, timing, yield, and manufacturability constraints.
• Collaborate with internal EDA team/external tool vendors to develop and optimize tools and methodologies.
• Must have 10+ years of experience in high-frequency processor physical design.
• Scripting skills (Python, Tcl, SKILL, etc.).
• Ability to work well in a team and be productive under aggressive schedules.
• Strong communication skills.
• Understanding of Agile development processes.
• Experience with Cadence Innovus, Tempus, Voltus, and/or IP integration (HBM, PCIe) for ASIC roles.
• Demonstrated ability to effectively team with a cross-site, multidisciplinary, international team.

Skills:

• Backend Physical Design
• ASIC
• Place & Route
• Cadence InnovTempus
• LVS/DRC
• Python is a plus

Benefits:

• Paid weekly!
• Health, Dental and Vision Insurance
• 401k

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.