Silicon Design Verification Engineer III
About Ascendion
Ascendion is a full-service digital engineering solutions company. We make and manage software platforms and products that power growth and deliver captivating experiences to consumers and employees. Our engineering, cloud, data, experience design, and talent solution capabilities accelerate transformation and impact for enterprise clients. Headquartered in New Jersey, our workforce of 11,000+ Ascenders delivers solutions from around the globe. Ascendion is built differently to engineer the next.
Ascendion | Engineering to elevate life
We have a culture built on opportunity, inclusion, and a spirit of partnership. Come, change the world with us:
- Build the coolest tech for world s leading brands
- Solve complex problems and learn new skills
- Experience the power of transforming digital engineering for Fortune 500 clients
- Master your craft with leading training programs and hands-on experience
Experience a community of change makers!
Join a culture of high-performing innovators with endless ideas and a passion for tech. Our culture is the fabric of our company, and it is what makes us unique and diverse. The way we share ideas, learning, experiences, successes, and joy allows everyone to be their best at Ascendion.
Job Title: Silicon Design Verification Engineer III
Key Responsibilities:
- Responsible for low power verification including both dynamic and static verification
- Write and augment existing testplans.
- Implement testbench and scoreboards / checkers
- Implement test sequences as per plan and debug failures
- Achieve 100% functional, code, and power coverage
- Work closely with designers, micro architects & f/w to resolve issues
- Ability to communicate & articulate clearly progress / issues with project leads
Minimum Qualifications:
- Bachelor degree in Electrical/Computer Engineering or Computer Science
- 7+ years of proven experience as a Design Verification engineer
- Hands on Experience with executable test plans and Coverage Driven verification
- Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology)
- Experience with low power verification (UPF) and experience with both static (i.e. VC LP) and dynamic (i.e. VCS NLP) power-aware verification flows
- Experience with UPF (Unified Power Format) based simulation flow
- Power and performance FPGA validation
- Experience with Power Aware GLS (Gate Level Simulation) flow
- 2+ Years of experience with C/C++
Preferred Qualifications:
- Master's Degree or PhD in Electrical/Computer Engineering or Computer Science or equivalent experience
- Hifi4, DSP (Digital Signal Processor), fixed point, floating point, python.
- TCL and Python (or similar) scripting language
- ASIC design experience
- Experience in formal property verification of complex compute blocks like DSP, CPU or HW accelerators
- Experience with complex SoCs
- Knowledge of coverage merging across simulation and formal
- Former FAANG or big tech preferred
Location: Remote [USA]
Salary Range: The salary for this position is between $176,800 $228,800 annually. Factors which may affect pay within this range may include geography/market, skills, education, experience, and other qualifications of the successful candidate.
Benefits: The Company offers the following benefits for this position, subject to applicable eligibility requirements: [medical insurance] [dental insurance] [vision insurance] [401(k) retirement plan] [long-term disability insurance] [short-term disability insurance] [5 personal days accrued each calendar year. The Paid time off benefits meet the paid sick and safe time laws that pertains to the City/ State] [10-15 days of paid vacation time] [6 paid holidays and 1 floating holiday per calendar year] [Ascendion Learning Management System]
Want to change the world? Let us know.
Tell us about your experiences, education, and ambitions. Bring your knowledge, unique viewpoint, and creativity to the table. Let s talk!
About Ascendion
Ascendion is a full-service digital engineering solutions company. We make and manage software platforms and products that power growth and deliver captivating experiences to consumers and employees. Our engineering, cloud, data, experience design, and talent solution capabilities accelerate transformation and impact for enterprise clients. Headquartered in New Jersey, our workforce of 11,000+ Ascenders delivers solutions from around the globe. Ascendion is built differently to engineer the next.
Ascendion | Engineering to elevate life
We have a culture built on opportunity, inclusion, and a spirit of partnership. Come, change the world with us:
- Build the coolest tech for world s leading brands
- Solve complex problems and learn new skills
- Experience the power of transforming digital engineering for Fortune 500 clients
- Master your craft with leading training programs and hands-on experience
Experience a community of change makers!
Join a culture of high-performing innovators with endless ideas and a passion for tech. Our culture is the fabric of our company, and it is what makes us unique and diverse. The way we share ideas, learning, experiences, successes, and joy allows everyone to be their best at Ascendion.
Job Title: Silicon Design Verification Engineer III
Key Responsibilities:
- Responsible for low power verification including both dynamic and static verification
- Write and augment existing testplans.
- Implement testbench and scoreboards / checkers
- Implement test sequences as per plan and debug failures
- Achieve 100% functional, code, and power coverage
- Work closely with designers, micro architects & f/w to resolve issues
- Ability to communicate & articulate clearly progress / issues with project leads
Minimum Qualifications:
- Bachelor degree in Electrical/Computer Engineering or Computer Science
- 7+ years of proven experience as a Design Verification engineer
- Hands on Experience with executable test plans and Coverage Driven verification
- Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology)
- Experience with low power verification (UPF) and experience with both static (i.e. VC LP) and dynamic (i.e. VCS NLP) power-aware verification flows
- Experience with UPF (Unified Power Format) based simulation flow
- Power and performance FPGA validation
- Experience with Power Aware GLS (Gate Level Simulation) flow
- 2+ Years of experience with C/C++
Preferred Qualifications:
- Master's Degree or PhD in Electrical/Computer Engineering or Computer Science or equivalent experience
- Hifi4, DSP (Digital Signal Processor), fixed point, floating point, python.
- TCL and Python (or similar) scripting language
- ASIC design experience
- Experience in formal property verification of complex compute blocks like DSP, CPU or HW accelerators
- Experience with complex SoCs
- Knowledge of coverage merging across simulation and formal
- Former FAANG or big tech preferred
Location: Remote [USA]
Salary Range: The salary for this position is between $176,800 $228,800 annually. Factors which may affect pay within this range may include geography/market, skills, education, experience, and other qualifications of the successful candidate.
Benefits: The Company offers the following benefits for this position, subject to applicable eligibility requirements: [medical insurance] [dental insurance] [vision insurance] [401(k) retirement plan] [long-term disability insurance] [short-term disability insurance] [5 personal days accrued each calendar year. The Paid time off benefits meet the paid sick and safe time laws that pertains to the City/ State] [10-15 days of paid vacation time] [6 paid holidays and 1 floating holiday per calendar year] [Ascendion Learning Management System]
Want to change the world? Let us know.
Tell us about your experiences, education, and ambitions. Bring your knowledge, unique viewpoint, and creativity to the table. Let s talk!