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Frontend Synthesis/STA Engineer

Salary undisclosed
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Job Title
Frontend Synthesis/STA Engineer

Job Summary
We are seeking an experienced Frontend Synthesis/STA Engineer to join our team. The ideal candidate will have expertise in digital circuit design, synthesis, and static timing analysis.

Key Responsibilities

1. Design and implement digital circuits using Verilog or VHDL.
2. Perform synthesis and optimization of digital designs.
3. Conduct static timing analysis (STA) to ensure design meets timing requirements.
4. Collaborate with cross-functional teams to resolve design and timing issues.
5. Develop and maintain scripts and tools for design automation.

Requirements

1. Bachelor's/Master's degree in Electrical Engineering, Computer Science, or related field.
2. 5+ years of experience in frontend synthesis and STA.
3. Strong understanding of digital circuit design, synthesis, and verification.
4. Proficiency in design languages (Verilog, VHDL) and synthesis tools (e.g., Synopsys Design Compiler, Cadence Genus).
5. Experience with static timing analysis tools (e.g., Synopsys PrimeTime, Cadence Tempus).
6. Strong programming skills in languages like Python, Perl, or Tcl.
7. Excellent problem-solving and communication skills.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
Report this job

Job Title
Frontend Synthesis/STA Engineer

Job Summary
We are seeking an experienced Frontend Synthesis/STA Engineer to join our team. The ideal candidate will have expertise in digital circuit design, synthesis, and static timing analysis.

Key Responsibilities

1. Design and implement digital circuits using Verilog or VHDL.
2. Perform synthesis and optimization of digital designs.
3. Conduct static timing analysis (STA) to ensure design meets timing requirements.
4. Collaborate with cross-functional teams to resolve design and timing issues.
5. Develop and maintain scripts and tools for design automation.

Requirements

1. Bachelor's/Master's degree in Electrical Engineering, Computer Science, or related field.
2. 5+ years of experience in frontend synthesis and STA.
3. Strong understanding of digital circuit design, synthesis, and verification.
4. Proficiency in design languages (Verilog, VHDL) and synthesis tools (e.g., Synopsys Design Compiler, Cadence Genus).
5. Experience with static timing analysis tools (e.g., Synopsys PrimeTime, Cadence Tempus).
6. Strong programming skills in languages like Python, Perl, or Tcl.
7. Excellent problem-solving and communication skills.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
Report this job