FPGA Engineer- Digital Modems
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Job Title: FPGA Engineer- Digital Modems
Job Location: Chandler Arizona 85226
Onsite Requirements:
- VHDL or Verilog
- Vivado
- Modems
Job Description:
Responsibilities:
- Design, develop, document, debug and test FPGA SoC systems; including:
- IP Integration into FPGA Projects (synthesis/implementation)
- High-Performance FPGA IP (VHDL/SystemVerilog)
- Userspace Drivers for FPGA IP (C++)
- Firmware for Embedded Microcontrollers (C)
- Utilize strong communication skills to effectively work and communicate with team members and engineering management.
Qualifications:
- Strong digital design engineer with FPGA/ASIC SoC design experience
- Strong FPGA Implementation with Altera Quartus or Xilinx Vivado
- Experience designing/debugging SoC systems with AMBA-compliant AXI and APB interfaces
- Experience designing fmax-optimized, high-throughput, pipelined AXI-Stream IP
- Capable of creating RTL simulations to identify and resolve most issues before hardware tests
- Knowledgeable in Static Timing Analysis (STA) and Synopsis Design Constraints (SDC)
- Experience analyzing STA reports and post-synth netlist/placement to resolve failing paths
- Experience contributing to schematic capture and layout for FPGA portions of PCB designs
- Experience implementing at least one Gigabit Transceiver Protocol:
- PCI Express, Interlaken, USB SuperSpeed
- 1000BASE-X/SGMII, 10GBASE-R, 40GBASE-R4, 100GBASE-R4
- Experience implementing Network Protocols, such as:
- L1: IEEE 802.3, Cisco, Q/SFP+ MSA standards for Ethernet (1G to 100G)
- L2/L3: IPv4, IPv6, ARP, ICMP, IGMP, UDP, TCP
- L4: VITA 49.2, IEEE-ISTO 4900 Digital IF Interoperability Standard (DIFI) and/or eCPRi (Highly Desired)
- Proficient in SW development with C, C++ and GIT version control
- Proficient in Microsoft Office Tools (Word, Excel, PowerPoint, Visio, etc.)
- Demonstrated experience supporting multi-disciplinary, cross functional and matrixed teams
Desired Skills:
- Working knowledge of digital IF streams such as VITA 49.2, DIFI and/or eCPRi (Highly Desired)
- Working knowledge of Embedded Linux: Kernel / Yocto / U-Boot / DeviceTree
- Working knowledge with SATCOM waveforms like DVB-S2X and/or 5G NTN 3GPP Rel 17/18
- Working knowledge of communication networks and security within a zero-trust environment
- Experience with Partial Reconfiguration/DFX or PCIe CvP
Education and Experience:
- Bachelors in Electrical or Computer Engineering (or related degree).
- 3+ years of FPGA/ASIC SoC design experience.
**3rd party and subcontract staffing agencies are not eligible for partnership on this position. 3rd party subcontractors need not apply.
- This position requires candidates to be eligible to work in the United States, directly for an employer, without sponsorship now or anytime in the future.
- This client is a US Federal Government contractor and is legally required to hire s.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
Report this job Job Title: FPGA Engineer- Digital Modems
Job Location: Chandler Arizona 85226
Onsite Requirements:
- VHDL or Verilog
- Vivado
- Modems
Job Description:
Responsibilities:
- Design, develop, document, debug and test FPGA SoC systems; including:
- IP Integration into FPGA Projects (synthesis/implementation)
- High-Performance FPGA IP (VHDL/SystemVerilog)
- Userspace Drivers for FPGA IP (C++)
- Firmware for Embedded Microcontrollers (C)
- Utilize strong communication skills to effectively work and communicate with team members and engineering management.
Qualifications:
- Strong digital design engineer with FPGA/ASIC SoC design experience
- Strong FPGA Implementation with Altera Quartus or Xilinx Vivado
- Experience designing/debugging SoC systems with AMBA-compliant AXI and APB interfaces
- Experience designing fmax-optimized, high-throughput, pipelined AXI-Stream IP
- Capable of creating RTL simulations to identify and resolve most issues before hardware tests
- Knowledgeable in Static Timing Analysis (STA) and Synopsis Design Constraints (SDC)
- Experience analyzing STA reports and post-synth netlist/placement to resolve failing paths
- Experience contributing to schematic capture and layout for FPGA portions of PCB designs
- Experience implementing at least one Gigabit Transceiver Protocol:
- PCI Express, Interlaken, USB SuperSpeed
- 1000BASE-X/SGMII, 10GBASE-R, 40GBASE-R4, 100GBASE-R4
- Experience implementing Network Protocols, such as:
- L1: IEEE 802.3, Cisco, Q/SFP+ MSA standards for Ethernet (1G to 100G)
- L2/L3: IPv4, IPv6, ARP, ICMP, IGMP, UDP, TCP
- L4: VITA 49.2, IEEE-ISTO 4900 Digital IF Interoperability Standard (DIFI) and/or eCPRi (Highly Desired)
- Proficient in SW development with C, C++ and GIT version control
- Proficient in Microsoft Office Tools (Word, Excel, PowerPoint, Visio, etc.)
- Demonstrated experience supporting multi-disciplinary, cross functional and matrixed teams
Desired Skills:
- Working knowledge of digital IF streams such as VITA 49.2, DIFI and/or eCPRi (Highly Desired)
- Working knowledge of Embedded Linux: Kernel / Yocto / U-Boot / DeviceTree
- Working knowledge with SATCOM waveforms like DVB-S2X and/or 5G NTN 3GPP Rel 17/18
- Working knowledge of communication networks and security within a zero-trust environment
- Experience with Partial Reconfiguration/DFX or PCIe CvP
Education and Experience:
- Bachelors in Electrical or Computer Engineering (or related degree).
- 3+ years of FPGA/ASIC SoC design experience.
**3rd party and subcontract staffing agencies are not eligible for partnership on this position. 3rd party subcontractors need not apply.
- This position requires candidates to be eligible to work in the United States, directly for an employer, without sponsorship now or anytime in the future.
- This client is a US Federal Government contractor and is legally required to hire s.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
Report this job