Chip-Level Timing Constraint Development Engineer
Salary undisclosed
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Role: Chip-Level Timing Constraint Development Engineer
Location: San Jose, CA
Onsite Role
JD:
As a Chip-Level Timing Constraint Development Engineer, you will be responsible for defining, developing, and validating timing constraints for complex ASIC designs at the chip level. Your role will involve close collaboration with cross-functional teams, including RTL designers, physical design engineers, and verification teams, to ensure robust timing closure and sign-off.
Key Responsibilities:
Develop and validate timing constraints (SDC) for chip-level designs, covering all functional and test modes.
Collaborate with RTL and architecture teams to understand design intent, clock structures, and interface requirements.
Perform static timing analysis (STA) to identify timing constraint gaps and modifiy to get 100% timing constraint coverage
Optimize timing constraints to achieve performance, power, and area (PPA) targets.
Debug and resolve timing issues related to clock domain crossings, multi-cycle paths, and false paths.
Develop and maintain scripts (TCL, Perl, Python) to automate timing constraint generation and validation.
Document timing methodologies and provide training to design teams on best practices.
[SHOULD] Work with physical design teams to ensure timing constraints are compatible with floorplanning, placement, and routing.
Develop and validate timing constraints (SDC) for chip-level designs, covering all functional and test modes.
Collaborate with RTL and architecture teams to understand design intent, clock structures, and interface requirements.
Perform static timing analysis (STA) to identify timing constraint gaps and modifiy to get 100% timing constraint coverage
Optimize timing constraints to achieve performance, power, and area (PPA) targets.
Debug and resolve timing issues related to clock domain crossings, multi-cycle paths, and false paths.
Develop and maintain scripts (TCL, Perl, Python) to automate timing constraint generation and validation.
Document timing methodologies and provide training to design teams on best practices.
[SHOULD] Work with physical design teams to ensure timing constraints are compatible with floorplanning, placement, and routing.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
Report this job Role: Chip-Level Timing Constraint Development Engineer
Location: San Jose, CA
Onsite Role
JD:
As a Chip-Level Timing Constraint Development Engineer, you will be responsible for defining, developing, and validating timing constraints for complex ASIC designs at the chip level. Your role will involve close collaboration with cross-functional teams, including RTL designers, physical design engineers, and verification teams, to ensure robust timing closure and sign-off.
Key Responsibilities:
Develop and validate timing constraints (SDC) for chip-level designs, covering all functional and test modes.
Collaborate with RTL and architecture teams to understand design intent, clock structures, and interface requirements.
Perform static timing analysis (STA) to identify timing constraint gaps and modifiy to get 100% timing constraint coverage
Optimize timing constraints to achieve performance, power, and area (PPA) targets.
Debug and resolve timing issues related to clock domain crossings, multi-cycle paths, and false paths.
Develop and maintain scripts (TCL, Perl, Python) to automate timing constraint generation and validation.
Document timing methodologies and provide training to design teams on best practices.
[SHOULD] Work with physical design teams to ensure timing constraints are compatible with floorplanning, placement, and routing.
Develop and validate timing constraints (SDC) for chip-level designs, covering all functional and test modes.
Collaborate with RTL and architecture teams to understand design intent, clock structures, and interface requirements.
Perform static timing analysis (STA) to identify timing constraint gaps and modifiy to get 100% timing constraint coverage
Optimize timing constraints to achieve performance, power, and area (PPA) targets.
Debug and resolve timing issues related to clock domain crossings, multi-cycle paths, and false paths.
Develop and maintain scripts (TCL, Perl, Python) to automate timing constraint generation and validation.
Document timing methodologies and provide training to design teams on best practices.
[SHOULD] Work with physical design teams to ensure timing constraints are compatible with floorplanning, placement, and routing.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
Report this job