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Jobs or company...

System IP Design Verification Engineer

Salary undisclosed
Checking job availability...
Original
Simplified

Title: Senior System IP Design Verification Engineer (Contract)
Duration: Through 09/12/2025
Pay: $90/hr $120/hr

Job Overview

We're looking for a Senior Staff System IP Design Verification Engineer to lead verification efforts for advanced System IP (coherent interconnects, caches). This is a hands-on role requiring deep experience in UVM, SystemVerilog, and gate-level simulation (GLS).

Key Responsibilities

  • Develop reusable testbenches and verification environments from scratch

  • Drive best practices and automation

  • Create and execute test plans, debug regressions, and close coverage

  • Perform GLS, power-aware (UPF) verification, and post-silicon support

  • Collaborate across design, SoC, and physical teams

Requirements

  • BS/MS/PhD in EE/CE and 12+ years of DV experience

  • Strong hands-on skills in UVM, SystemVerilog, GLS (5+ years), and scripting

  • Familiarity with ARM protocols (CHI, AXI, etc.)

  • Experience in IP bring-up, silicon debug, and low-power verification

  • Excellent debugging, collaboration, and communication skills

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
Report this job

Title: Senior System IP Design Verification Engineer (Contract)
Duration: Through 09/12/2025
Pay: $90/hr $120/hr

Job Overview

We're looking for a Senior Staff System IP Design Verification Engineer to lead verification efforts for advanced System IP (coherent interconnects, caches). This is a hands-on role requiring deep experience in UVM, SystemVerilog, and gate-level simulation (GLS).

Key Responsibilities

  • Develop reusable testbenches and verification environments from scratch

  • Drive best practices and automation

  • Create and execute test plans, debug regressions, and close coverage

  • Perform GLS, power-aware (UPF) verification, and post-silicon support

  • Collaborate across design, SoC, and physical teams

Requirements

  • BS/MS/PhD in EE/CE and 12+ years of DV experience

  • Strong hands-on skills in UVM, SystemVerilog, GLS (5+ years), and scripting

  • Familiarity with ARM protocols (CHI, AXI, etc.)

  • Experience in IP bring-up, silicon debug, and low-power verification

  • Excellent debugging, collaboration, and communication skills

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
Report this job