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ASIC Timing Engineer

Salary undisclosed

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Job Title: Chip-Level Timing Constraint Development Engineer
Location: San Jose, CA - You must be already located in the San Jose area.
Duration: 12+ Months
Visa: Open (No restrictions)

Responsibilities:

5 years of experience...

  • Define, develop, and validate timing constraints (SDC) for complex chip-level ASIC designs

  • Perform static timing analysis (STA) to ensure full timing coverage and closure

  • Collaborate with RTL, architecture, and physical design teams on clock structures and design intent

  • Optimize constraints to meet performance, power, and area (PPA) goals

  • Debug timing issues: clock domain crossings, multi-cycle paths, and false paths

  • Write and maintain automation scripts using TCL, Perl, and Python

  • Document timing methodologies and train design teams on best practices

  • Ensure constraint compatibility with floorplanning, placement, and routing

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
Report this job

Job Title: Chip-Level Timing Constraint Development Engineer
Location: San Jose, CA - You must be already located in the San Jose area.
Duration: 12+ Months
Visa: Open (No restrictions)

Responsibilities:

5 years of experience...

  • Define, develop, and validate timing constraints (SDC) for complex chip-level ASIC designs

  • Perform static timing analysis (STA) to ensure full timing coverage and closure

  • Collaborate with RTL, architecture, and physical design teams on clock structures and design intent

  • Optimize constraints to meet performance, power, and area (PPA) goals

  • Debug timing issues: clock domain crossings, multi-cycle paths, and false paths

  • Write and maintain automation scripts using TCL, Perl, and Python

  • Document timing methodologies and train design teams on best practices

  • Ensure constraint compatibility with floorplanning, placement, and routing

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
Report this job