Verification Engineer
Salary undisclosed
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Role Responsibilities:
1. As member of our verification team, you'll understand the design & implementation with focus on memory subsystem, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), implement test/coverage plans, and verify the correctness of the design.
2. Collaborate with architects, designers, software engineers across sites to accomplish your goals.
3. Plan and work on strategic direction of the methodology for the testbench with advance methodology.
Required Qualifications:
1. You have Bachelors in Electrical Engineering.
2. Exposure to Computer Architecture, ASIC design and verification methodology is required.
3. Strong ability with SystemVerilog, C and/or C++, test planning, coverage closure, and creating reusable verification components.
4. Knowledgeable in constrained random testing with functional coverage and assertion-based verification.
5. Understanding of object oriented programming concepts.
6. Exposure to simulation tools like VCS, IES and debug tools like Debussy, GDB.
7. Strong interpersonal skills.
8. Good debugging and problem solving skills.
Compensation: 92,000 USD - 178,250 USD
About us:
We are an internationally recognized HR consultancy firm helping candidates match with the potential roles by using an Artificial Intelligence System which is free of cost. We are a global market leader who works with several top-tier companies, tech startups, freelancers, industry professionals, and subject matter experts for projects, internships, and jobs.
Important:
The successful application submission for the above role(s) will be conditional to your profile evaluation by our AI system. We can let you know better once you submit your resume.
1. As member of our verification team, you'll understand the design & implementation with focus on memory subsystem, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), implement test/coverage plans, and verify the correctness of the design.
2. Collaborate with architects, designers, software engineers across sites to accomplish your goals.
3. Plan and work on strategic direction of the methodology for the testbench with advance methodology.
Required Qualifications:
1. You have Bachelors in Electrical Engineering.
2. Exposure to Computer Architecture, ASIC design and verification methodology is required.
3. Strong ability with SystemVerilog, C and/or C++, test planning, coverage closure, and creating reusable verification components.
4. Knowledgeable in constrained random testing with functional coverage and assertion-based verification.
5. Understanding of object oriented programming concepts.
6. Exposure to simulation tools like VCS, IES and debug tools like Debussy, GDB.
7. Strong interpersonal skills.
8. Good debugging and problem solving skills.
Compensation: 92,000 USD - 178,250 USD
About us:
We are an internationally recognized HR consultancy firm helping candidates match with the potential roles by using an Artificial Intelligence System which is free of cost. We are a global market leader who works with several top-tier companies, tech startups, freelancers, industry professionals, and subject matter experts for projects, internships, and jobs.
Important:
The successful application submission for the above role(s) will be conditional to your profile evaluation by our AI system. We can let you know better once you submit your resume.
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