DFT (Design for Test) Lead

Job Title: DFT (Design for Test) Lead

Location: Santa Clara, CA

Duration /Term: Long Term Contract

Open to: C2C (Corp-to-Corp) Candidates

Job Description:

• We are seeking a knowledgeable and experienced DFT (Design for Test) Lead to join our team in Santa Clara, CA. The ideal candidate will have a strong background in testability techniques and DFT methodologies for digital logic designs and embedded memories.

Key Responsibilities:

• Apply testability techniques and features such as SSN, Compressed Scan, Built-in Self-Test (BIST), and Boundary Scan within the digital logic domain.
• Utilize JTAG, 1500, and 1687 networks effectively; knowledge of BSDL, ICL, and PDL is preferable.
• Lead DFT RTL insertion processes, Automated Test Pattern Generation (ATPG), and coverage analysis; proficiency in zero-delay and SDF-based pattern simulations is essential.
• Demonstrate expertise in using Mentor DFT tools, specifically Tessent Shell.
• Possess a solid understanding of Verilog and logic design principles.
• Implement scripting solutions using TCL, Python, or other scripting languages such as Perl to enhance automation and efficiency in DFT processes.

Qualifications:

• Strong experience in DFT techniques and methodologies.
• Familiarity with embedded memory testability and digital logic testing.
• Excellent problem-solving skills and the ability to work collaboratively within a team.
• Effective communication skills to liaise with cross-functional teams.

Key Skills : Design for Test (DFT) principles, DFT Techniques and Methodologies, Embedded Memory Testability, Digital Logic Testing

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