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ASIC Physical Design Engineer

Salary undisclosed

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Role: ASIC Physical Design Engineer

Work Location: San Francisco Area

JOB DESCRIPTION



Physical Design Engineer



Job Responsibility

Chip level floor planning, partitioning, timing budget generation, power planning, top-level PnR, CTS, block integration and ECO generation.

Expertise in timing closure (STA) of high frequency blocks

Handling blocks of high instance counts and complex designs 1M+ instances and clock frequencies about 1 GHz

Experience with low power implementation and signoff, power gating, multiple voltage rails, UPF knowledge.

Experience in Block-level and Full-chip integration.





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