Semiconductor Design Engineer
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One of our Global Partners and lead producer in computer memory and computer data storage is looking for a Semiconductor Design Engineer to join their team in Boise, ID. This Engineer is responsible for custom level design down to the transistor and/or gate level for Digital Desings/Digital Circuits. This includes simulating, optimizing, and floor planning for DRAM circuits. This role will fill a critical need on the team to help proactively design next generation products that are optimized for manufacturing and assure the best cost, quality, reliability, time-to-market, and customer satisfaction possible. Relocation packages offered & sponsorship available for this FTE opportunity! Apply today to connect with a team member on more details!
REQUIREMENTS:
- 5+ years of experience designing and developing memory products
- Assisting with overall design, layout, and optimization of memory circuits
- Experience performing circuit simulations using digital deign tools standard industry tools such as Cadence Virtuoso, Mentor Graphics Calibre for DRC/LVS/PV, Synopsys Star RC for parasitic extraction, etc.
- Experience use of tools for Custom Design Flows.
- Extensive knowledge of layout design, CMOS Circuit Design, and Device Physics
- Experience debugging circuits based on both simulation and silicon results.
- Strong understanding of high-speed logic and clock design
- Bachelor of Science in Electrical Engineering
PREFERRED SKILLS:
- Master of Science in Electrical Engineering
- SRAM (Static Random Access Memory) experience
RESPONSIBILITIES:
- Lead the creation of circuit solutions with a strong focus on Design for Manufacturability (DFM). Define technical requirements to ensure performance and manufacturability, and proactively address potential issues early in the design process.
- Seek out and implement groundbreaking ideas to enhance our solutions. Stay ahead of industry trends and propose innovative approaches that differentiate our offerings from the competition.
- Contribute to the design and development of key schematic blocks such as memory arrays, control logic, address decoders, data paths, and internal test logic. Ensure these components are accurate, efficient, and well-integrated.
- Understand and assess how architectural decisions affect power consumption, speed, and die size. Optimize designs to balance performance, efficiency, and cost effectively.
- Import layout parasitic data into the simulation environment to achieve accurate and realistic results, ensuring that designs perform reliably under actual conditions.
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