Design Verification Methodology Engineer - (UVM/SV)

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THE ROLE:

The AMD Verification Methodology and Technology (VMT) team delivers verification methodology and technology for all AMD teams and products. Team member will be working with global teams on the verification methodologies and technologies covering design technology, functional verification technology, coverage, debug, low power technology, and automation methodologies.

THE PERSON:

A successful candidate in this senior position is expected to excel in analytical thinking, problem solving, organizing data, gathering requirements, planning and execution. He/she needs to be a self-starter who collaborates well with team members and customers alike to successfully drive tasks to completion.

KEY RESPONSIBILITIES:

The successful candidate will assume technical responsibilities and hands-on technical architect role responsible for providing complex design methodologies in the hardware design verification space. The following is a list of key responsibilities that the candidate will assume:

• Be a part of a wider team of technical experts in design verification in AMD's Central R&D team
• Collaborate with the arch, functional DV and various design teams to understand design enhancement and verification ask
• Play an expert role in AMD's verification flow by defining roadmaps and creating methodologies for DV, VIPs, UVCs, and BFMs for both simulation and emulation.
• Lead verification methodologies with expertise in UVM/Systemverilog based testbenches.
• Develop UVM testbench components including stimulus, drivers, BFMs, behavioral models, monitors and checkers
• Experience in functional and code coverage methodology for faster coverage closure
• Demonstrate and utilize strong debugging skills in SOC/IP design & verification
• knowledge of C/C++ based testbench architecture
• Conduct simulation performance analysis to support growing design complexities.
• Collaborate with EDA vendors for tool trainings, evaluation and drive EDA vendors toward common solutions across AMD

PREFERRED EXPERIENCE:

• Proficient in SoC/sub-system/IP level verification
• Experienced with Verilog, System Verilog, C, and C++
• Proficient in using UVM testbenches
• Knowledge of Perl/Python/Ruby and other scripting languages
• knowledge of industry standard tools for DV, VIPs, etc. expected
• Experience in EDA industry tools, scripting and software development practices
• Hardware/software co-verification and validation methodologies is a plus
• Emulation and/or simulation acceleration experience is a plus
• Must possess strong interpersonal and communication skills and needs to be a team player

ACADEMIC CREDENTIALS:

• Bachelors, Master, or PhD degree in Electrical or Computer engineering

LOCATION: Santa Clara, CA

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At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD's Employee Stock Purchase Plan. You'll also be eligible for competitive benefits described in more detail here .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.