RTL Development Engineer (FPGA Expert)
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Overview:
We are seeking an experienced RTL (Register Transfer Level) Development Engineer with expertise in FPGA design and extensive knowledge of Xilinx/AMD tools, including Vivado.
The successful candidate will play a critical role in the design, development, verification, and implementation of FPGA-based solutions for
complex systems.
This role requires a deep understanding of FPGA architecture, RTL design, simulation, and synthesis, as well as proficiency in Vivado for hardware design, debugging, and verification.
Key Responsibilities:
1. RTL Design and Implementation:
o Design, develop, and optimize RTL code in VHDL/Verilog/SystemVerilog for FPGA-based
systems.
o Develop efficient, modular, and reusable RTL architectures for high-performance, low- power, and scalable systems.
o Implement complex algorithms and digital signal processing (DSP) blocks for FPGA
targets.
o Perform RTL coding for custom IP cores and integration of third-party IP cores as per
projectrequirements.
2. FPGA Synthesis and Place-and-Route:
o Utilize Xilinx Vivado for synthesis, timing closure, and place-and-route of FPGA designs.
o Optimize FPGA resource utilization, timing, power, and area to meet design constraints
and specifications.
o Perform static timing analysis (STA) and ensure designs meet timing closure across all
operating conditions.
3. Verification and Debugging:
o Create testbenches and verify RTL designs using simulation tools such as ModelSim, uesta, or Xilinx XSim.
o Perform pre-silicon verification, including functional and timing verification at RTL and
gate-level.
o Debug designs using simulation, logic analyzers, and in-circuit testing tools such as Vivado
ILA (Integrated Logic Analyzer) and Chipscope.
4. Vivado Toolchain Expertise:
o Utilize Vivado s IP integrator to build complex FPGA systems using standard and custom
IPs.
o Work with Vivado HLS (High-Level Synthesis) to convert high-level algorithms (C/C++) into
RTL for FPGAs.
o Develop scripts for automation using TCL and other scripting languages within the Vivado
environment.
o Use Vivado s bitstream generation and device programming tools to configure FPGAs.
5. System-Level Design:
o Design FPGA-based systems that integrate with microprocessors, DSPs, or custom
hardware.
o Work on SoC platforms such as Zynq/Zynq UltraScale+ by leveraging Xilinx tools to create
hardware-software co-designs.
o Collaborate with firmware, software, and hardware teams to integrate FPGAs into larger
systems and platforms.
6. Documentation and Compliance:
o Create and maintain detailed documentation, including design specifications, block
diagrams, and verification plans.
o Ensure designs are compliant with industry standards and specific project requirements.
o Work with teams on version control and design management using tools like Git.
7. Collaboration and Leadership:
o Provide technical guidance and mentorship to junior FPGA engineers.
o Work closely with cross-functional teams, including hardware, software, and product
engineering teams.
o Communicate effectively with stakeholders to discuss project progress, challenges, and
technical decisions.
Required ualifications:
Education: Bachelor's or Master s degree in Electrical Engineering, Computer Engineering, or a
Education: Bachelor's or Master s degree in Electrical Engineering, Computer Engineering, or a
related field. Experience:
o 10+ years of hands-on experience in RTL design for FPGAs, including Xilinx/AMD devices.
o Extensive experience with Xilinx Vivado Design Suite, including synthesis, simulation, and debugging.
o Solid understanding of FPGA architecture, timing analysis, and clock domain crossing
o Extensive experience with Xilinx Vivado Design Suite, including synthesis, simulation, and debugging.
o Solid understanding of FPGA architecture, timing analysis, and clock domain crossing
(CDC) techniques.
o Expertise in VHDL/Verilog/SystemVerilog coding for RTL design.
o Experience with FPGA verification methodologies (simulation, constrained random testing, etc.).
o Expertise in VHDL/Verilog/SystemVerilog coding for RTL design.
o Experience with FPGA verification methodologies (simulation, constrained random testing, etc.).
- Preferred ualifications:
Experience with Xilinx Zynq SoC (including Zynq UltraScale+) for hardware-software integration. - Proficiency in Vivado HLS (High-Level Synthesis) and familiarity with C/C++ algorithm conversion
- into hardware.
- Familiarity with industry standards such as AXI, PCIe, Ethernet, or other high-speed interfaces.
- Knowledge of FPGA design for signal processing, communication systems, or AI/ML accelerators.
- Familiarity with TCL scripting and automation in Vivado.
- Experience with embedded system design and development.
- Personal Attributes:
- Strong problem-solving skills and the ability to troubleshoot complex digital designs.
- Excellent communication skills, both written and verbal.
- Ability to work in a team and independently with minimal supervision.
- Strong attention to detail and ability to document designs and processes thorough.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
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